1. Field of the Invention
The present invention generally relates to static type semiconductor memory devices, and more particularly, to a static type semiconductor memory device having a power circuit for test mode, and an operating method thereof.
2. Description of the Background Art
SRAM's (Static Random Access Memories) are one type of semiconductor memory devices. Since a memory cell of a SRAM is comprised of MOSFET's (insulated gate field effect transistors) only or of a flip-flop of MOSFET's and resistance elements, storage information in the SRAM will not disappear with the lapse of time while power supply is on. In the SRAM's, therefore, there is no need for rewriting, or refreshing storage information, as is required in DRAM's (Dynamic Random Access Memories). Also with the SRAM's, generally, a lower consumption power for operation and data holding, and a higher-speed operation can be achieved. Due to these advantages, the SRAM's are used in a variety of fields.
FIG. 10 is a schematic block diagram showing a typical structure of an SRAM. Referring to the diagram, the SRAM comprises a memory cell array 101 having a plurality of memory cells arranged in a matrix, word lines provided each corresponding to one row, and bit line pairs provided each corresponding to one column, and an X address buffer decoder 102 and a Y address buffer decoder 103 which put only a memory cell to be selected in a data writable or readable state by amplifying and decoding a row address signal and a column address signal, respectively, for selecting the memory cell located in the memory cell array 101 to and from which data is written in and read out. The SRAM further comprises an R/W control circuit 104 responsive to a read and write signal R/W which designates either data writing or reading mode for the selected memory cell, for setting a read and write amplifier 105 and a data output buffer 106 which will be described later in the mode designated by the read and write signal R/W, and in data writing, applying input data Din to be written in to the read and write amplifier 105, the read and write amplifier 105 for, in data reading, amplifying the data read out from the selected memory cell and applying the amplified data to the data output buffer 106, and in data writing, amplifying the input data Din applied through the R/W control circuit 104 and outputting the amplified data to the memory cell array 101, and the data output buffer 106 for further amplifying the read-out data received from the read and write amplifier 105 in data reading and outputting the thus amplified data to the outside as output data Dout.
In data writing, the input data outputted from the read and write amplifier 105 is applied to the bit line pair corresponding to the selected memory cell in the memory cell array 101. In data reading, the storage data of the selected memory cell in the memory cell array 101 appear on the corresponding bit line pair to be applied to the read and write amplifier 105 as read-out data.
FIG. 11 is a circuit diagram showing structure of one-column memory cells in the memory cell array 101 of FIG. 10. Referring to the diagram, the structure will be described below.
In the diagram, between two bit lines 23 and 24 constituting one bit line pair, there are provided a plurality of memory cells 21a to 21n. The memory cells 21a to 21n are configured in the same manner. Taking now the memory cell 21a as an example, it is comprised of two N-channel MOSFET's as an inverter (referred to as inverter transistors hereinafter) 38a and 39a, two high load resistances 40a and 41a, and two N-channel MOSFET's for access (referred to as access transistors hereinafter) 36a and 37a. The drains of the inverter transistors 38a and 39a are connected at storage nodes N10a and N11a, respectively, to one-side ends of the load resistances 40a and 41a which are formed of polysilicon or the like to have high resistance values, while the other ends of the resistances 40a and 41a are connected to supply potential Vcc for driving the memory cell. The sources of these inverter transistors 38a and 39a are connected to ground potential GND through a ground potential line ls. The inverter transistor 38a has its gate connected to the storage node N11a and the inverter transistor 39a has its gate connected to the storage node N10a. The storage data are stored as potential at parasitic capacitances existing between the ground potential GND and the storage nodes N10a and N11a, respectively. The storage node N10a is connected to the bit line 23 through the access transistor 36a, which has its gate connected to the corresponding word line 25a among other word lines 25b to 25n. The storage node N11a is connected to the bit line 24 through the access transistor 37a, which has its gate connected to the corresponding word line 25a.
The bit lines 23 and 24 are connected to input/output lines 32 and 33, respectively, through MOSFET's 30 and 31, the gates of which receive a column select signal Y.sub.0 from the Y address buffer decoder 103 (FIG. 10). The word lines 25a to 25n receive row select signals X.sub.0 to X.sub.n, respectively, from the X address buffer decoder 102 (FIG. 10). Further, the bit lines 23 and 24 are connected through diode-connected bit line loading MOSFET's 28 and 29 to a connection line 22 to which supply potential Vcc is applied. These MOSFET's 28 and 29 are provided for precharging the bit lines 23 and 24. That is, the bit lines 23 and 2 are raised to Vcc-Vth, a potential lower than the supply potential Vcc by the threshold voltage Vth of the MOSFET's 28 and 29.
Subsequently, operation of such a memory cell will be described. Assume now that data stored in the memory cell 21a is to be read out with the node N10a at the low level and the node N11a at the high level. In this case, potential of the row select signal X.sub.0 applied to the word line 25a rises from the unselected level of about 0V to substantially Vcc. As a result, current flows through the connection line 22, the bit line loading MOSFET 28, the access transistor 36a and the inverter transistor 38a, to the ground potential GND. Since the inverter transistor 39a is non-conductive, however, current flow does not occur through a path linking the connection line 22, the bit line loading MOSFET 29, the access transistor 37a and the inverter transistor 39a, to the ground potential GND. Accordingly, the bit line 23 is set to a potential depending on the on-resistance ratio between the MOSFET's 28, 36a and 38a, while the bit line 24 remains set at the potential lower than the supply potential Vcc by the threshold voltage of the bit line loading MOSFET 29. The data is read out based on the detection of the potential difference which appears between the two bit lines of this bit line pair.
In such SRAM's also, a larger storage capacity, or a larger number of memory cells on one chip has been pursued. Therefore, it has been required to arrange memory cells on a semiconductor substrate with a highest possible density. In forming memory cells on a semiconductor substrate under such conditions, the layout is made such that the area occupied by an interconnection layer is as small as possible on the substrate.
FIG. 12 is a circuit diagram showing structure of the memory cell of FIG. 11 in the form approximate to a laid out pattern on a semiconductor substrate. Referring to the diagram, both of the inverter transistors 38a and 39a are provided with their gates extending along the ground line ls. The access transistors 36a and 37a are provided in the upper portion of the diagram with respect to the inverter transistors 39a and 38a, respectively. The power supply line lv to which the supply potential Vcc is applied is provided in parallel with the ground line ls. Therefore, the resistors 40a and 41a are provided on the sides of the inverter transistors 38a and 39a, respectively.
FIG. 13 is a partial plan view showing a typical layout for the memory cell shown in FIG. 11 to be practically formed on a P-type semiconductor substrate. FIGS. 14A and 14B are sectional views of a memory cell formed in the layout of FIG. 13 and taken along lines A-B and C-D in FIG. 13. In the diagrams, numerals and characters parenthesized with ( ) represent the corresponding portions in FIG. 11.
As shown in FIG. 13, the word line 25a is formed of the same first polycrystalline silicon layer (hatching portion) as forming gates 110 and 120 of the access transistors 36a and 37a. Also, gates 130 and 140 of the inverter transistors 39a and 38a are formed of the first polycrystalline silicon layer. It is to be noted here, however, that the portion of the first polycrystalline silicon layer forming the gates 130 and 140 of the inverter transistors 39a and 38a is not connected to the portion of the same forming the gates 110 and 120 of the access transistors 36a and 37a. The interconnection lv for connecting the supply potential Vcc and the high resistances 40a and 41a, and the high resistances 40a and 41a are formed of a second polycrystalline silicon layer (enclosed by solid line). As shown in FIG. 14A, the high resistance 40a is located over the gate 130 of the inverter transistor 39a. The gate 130, the source 230 and the drain 330 of the inverter transistor 39a and the resistor 40a are insulated by an insulating film formed of SiO.sub.2. Likewise, the resistor 41a is formed above the inverter transistor 38a with an insulating film extending therebetween. A cross-coupling interconnection for connecting the drain 330 of the inverter transistor 39a and the gate 140 of the inverter transistor 38a shares an n.sup.+ -diffused layer region (enclosed by dotted line) with a source 220 and a drain 320 of the access transistor 37a. A cross-coupling interconnection for connecting the gate 30 of the inverter transistor 39a and a drain 340 of the inverter transistor 38a is formed of a second polycrystalline silicon layer connected in a region 410 to both the first polycrystalline silicon layer forming the gate 130 of the inverter transistors 39a and to the n.sup.+ -diffused layer region forming the source 220 and the drain 320 of the access transistor 37a. The storage nodes N10a and N11a are formed as regions 420 and 430, respectively, where the first and the second polycrystalline silicon layers and the n.sup.+ -diffused layer region overlap one upon another. As shown in FIG. 14B, the portion of the second polycrystalline silicon layer forming the interconnection lv between the supply potential Vcc and the high resistances 40a and 41a is connected to the supply potential Vcc, and the portion of the n.sup.+ -diffused layer region forming the sources 230 and 240 of the inverter transistors 39a and 38a is connected to the ground potential GND. Therefore, the ground line ls is formed of the n.sup.+ diffused layer. Also the power supply line lv and the ground line ls are insulated from each other by the insulating film formed of SiO.sub.2. In FIGS. 14A and 14B, SOP represents an isolation region.
Other memory cells unshown in FIG. 11 are also formed on the semiconductor substrate in the layout as shown in FIG. 13, where the sources of the two inverter transistors contained in one memory cell and those of the memory cells adjacent to the former in the column direction are formed of a common impurity-diffused layer. In FIG. 11, therefore, the sources of the transistors 38a and 39a in the memory cell 21a and those in the memory cell adjacent to the former on its upper side are connected through the connection line ls formed of the impurity-diffused layer. Therefore, in the memory cell 21a and the memory cell adjacent thereto in the column direction, connection nodes between the sources of the corresponding inverter transistors are represented in FIG. 13 as portions N50 and N51 of the impurity-diffused layer forming the ground line ls. Meanwhile, the impurity-diffused layer forming the ground line ls is shared by memory cells arranged in the same row. Accordingly, also the sources of the inverter transistors in the memory cells adjacent in the row direction are connected by the impurity-diffused layer.
As described above, the connection line ls to which the ground potential GND is to be applied is formed of the same impurity-diffused layer as forming the sources of the inverter transistors 38a and 39a. In FIG. 11, therefore, the sources of the inverter transistors 38a and 39a are connected to the ground potential GND practically through resistance of the impurity-diffused layer.
FIG. 15 is a circuit diagram showing an equivalent circuit of two memory cells adjacent in the column direction, taking this resistance into consideration. In the diagram, circuit structure of memory cells 21a and 21b and their peripheral portions is the same as that shown in FIG. 11. The sources of the inverter transistors 38a and 38b corresponding to each other in the adjacent memory cells 21a and 21b are connected at a node N50 formed of the same impurity-diffused layer as forming those sources, to be further connected to ground potential GND through a resistance 50 of the impurity-diffused layer. Likewise, the sources of the inverter transistors 39a and 39b are connected at another node N51 formed of the same impurity-diffused layer as forming those sources, to be further connected to the ground potential GND through resistances 50 and 51 of the impurity-diffused layer. Another resistor 52 also represents resistance of the impurity-diffused layer forming the connection line ls, and is connected to the sources of the inverter transistors contained in the memory cells adjacent to the memory cells 21a and 21b, respectively, in the row direction.
Assume now that the word line 25b is selected when potential of the nodes N10a and N11a in the memory cell 21a are at the high and the low levels, respectively, and also potential of the nodes N10b and N11b in the memory cell 21b are at the high and the low levels, respectively. The following description will be made with reference to FIG. 2 as well. FIG. 2 is a diagram showing potential change at the nodes N 10a, N11a and N51, respectively, in the case described above, where the axis of abscissas represents time and the axis of ordinates represents potential. Meanwhile, since FIG. 2 shows both cases of a conventional SRAM and that of an embodiment, reference to the diagram will be made again in "Description of the Preferred Embodiments".
In this case, when the word line 25b is selected, the access transistors 36b and 37b in the memory cell 21b are rendered conductive. At this moment, the inverter transistor 39b is in the conductive state due to the high-level potential of the node N10b, while the inverter transistor 38b is in the non-conductive state due to the low-level potential of the node N11b. This causes current flow of about 0.15 mA from the supply line 22 to the ground potential source GND through a path linking the bit line loading transistor 29, the bit line 24, the access transistor 37b the inverter transistor 39b, the resistance 51 and the resistance 50. Resistance value of the resistance 51 is about 100 .OMEGA.. Therefore, between the nodes N50 and N51, there occurs a voltage drop of about 0.15 mA .times. 100 .OMEGA., or 15 mV due to the resistance 51. Accordingly, the source potential of the inverter transistors 38a and 39a and the inverter transistors 38b and 39b in practice does not become equal to the ground potential GND. As a result, the source potential of the inverter transistors 39a and 39b (potential of the node N51) becomes higher than that of the inverter transistors 38a and 38b (potential of the node N50) by about 15 mV and thus above the ground potential GND, as shown in FIG. 2(c). Since at this moment, the inverter transistor 39a in the memory cell 21a is in the conductive state due to the high-level potential of the node N10a, the potential rise at the node N51 is transmitted to the node N11a through the inverter transistor 39a. As a result, also the potential of the node N11a becomes about 15 mV as shown in FIG. 2(c). The potential thus raised of the node N11a is applied to the gate of the inverter transistor 38a which has been in the non-conductive state due to the previous low-level potential of the node N11a. A normal MOSFET is not rendered conductive by such a gate potential rise of about only 15 mV. Therefore, if the inverter transistor 38a has been properly fabricated, it can be held in the non-conductive state irrespective of the potential rise at the node N11a. However, if the inverter transistor 38a has an abnormal low threshold voltage due to some defect caused in its fabrication process, the potential rise at the node N11a brings the transistor 38a into a lightly conductive state. The lightly conductive inverter transistor 38a has a significant conducting resistance, while the resistance 40a has been set to have a considerably large resistance value of about 10.sup.12 .OMEGA. so as to reduce stand-by current of the SRAM. Therefore, when the conducting resistance of the lightly conductive inverter transistor 38a gets to approximately the same value as the resistance value of the resistance 40a, the high-level potential Vcc of the node N10a is reduced to a lower value which is obtained by dividing the voltage between the supply potential Vcc and the node N50 according to the ratio between the resistance 40a and the conducting resistance of the lightly conductive inverter transistor 38a. This means that the node N10a is discharged through the lightly conductive inverter transistor 38a. This discharge occurs at a speed depending on a time constant which is determined by the product of the parasitic capacitance value of the node N10a and the conducting resistance of the lightly conductive inverter transistor 38a. Therefore, if the inverter transistor 38a has any defect, the potential rise at the node N11a causes potential fall of the node N10a to begin at the time t0 as indicated by 2 in FIG. 2(a), and at a discharging speed determined by the time constant described above. When the potential of the node N10a falls below the threshold voltage Vth of the inverter transistor 39a at the time t2, the inverter transistor 39a is brought from the conductive state into the non-conductive state so that the potential of the node N11a begins to rise due to the supply potential Vcc. Following this, the lightly conductive inverter transistor 38a is rendered completely conductive, so that the potential of the node N10a begins to fall more sharply toward the ground potential GND. As a result, the potential of the node N11a begins to rise at the time t2, as indicated by 4 in FIG. 2(b). By contrast, the potential of the node N10a begins to fall more sharply than before at the time t2, as indicated by 2 in FIG. 2(a). That is, after the time t2, the two inverter transistors 38a and 39a in the memory cell 21a are inverted in their state (conductive/non-conductive). This means that the storage data in the memory cell 21a begins to be inverted. As a result, the potential difference between the nodes N10a and the N11a becomes small. As previously described, data reading from a memory cell is effected by detecting the potential difference between the two storage nodes of the memory cell, through the corresponding bit line pair. Therefore, if the memory cell 21b remains in the selected state for more than the time period t2 to t0 which is taken between the beginning of the potential fall at the node N10a and the beginning of the data inversion in the memory cell 21a, the potential difference between the nodes N10a and N11a becomes considerably small. If the data in the memory cell 21a is to be read out thereafter, therefore, the storage data nay be inverted before read out, and this means malfunction of the SRAM.
Assume next that the memory cells 21a and 21b have storage data contrary to those in the case described above, or the potential of the nodes N10 and N11a in the memory cell 21a is at the low and the high levels, respectively, and the potential of the nodes N10b and N11b in the memory cell 21b is at the low and the high levels, respectively. In this case, if the inverter transistor 39a has an abnormal low threshold voltage, the potential of the node N11a falls as the data in the memory cell 21b is read out, causing the same phenomena as in the case described above.
Contrary to the two cases above, if data is read out from the memory cell 21a with the inverter transistor 38b or 39b in the memory cell 21b having an abnormal low threshold voltage, such inversion of storage data will occur in the memory cell 21b.
As has been described above, if an inverter transistor has any defect, the potential difference between the two storage nodes in the memory cell containing the defective inverter transistor is reduced in case of data reading from any other memory cell adjacent to the memory cell in the column direction. This leads to malfunction of the SRAM. Therefore, a completed SRAM has to be examined as to whether or not each memory cell contains inverter transistors with normal threshold voltage. For this reason, SRAM's are subject to a test after fabrication. The test is conducted to identify such phenomena as described above in the following manner. That is, the identical data is in advance stored in two memory cells adjacent to each other in the column direction and then one memory cell is put in the selected state for a certain time. Subsequently, the data in the other memory call adjacent in the column direction is read out and examined as to whether or not it is the same data as that stored in advance. In the following, the test as described above is called a disturb test. The certain time as described above should be set long enough for the potential of a storage node to fall, due to any defect in an inverter transistor, to a value which might cause malfunction of the SRAM. The time required for the potential fall of the storage node due to the defective inverter transistor is substantially equal to a discharge time constant .tau. which is given by the product of R .times. C, where C represents the parasitic capacitance value of the storage node and R represents the conducting resistance value of the inverter transistor connected to the storage node. Since the parasitic capacitance of a storage node is generally about 0.1 pF, if the conducting resistance value of the lightly conductive inverter transistor is about 10.sup.12 .OMEGA., the certain time as described above is 0.01 pF .times. 10.sup.12 .OMEGA., or about 10 ms. Thus, it is examined in about 10 ms whether or not one of the two inverter transistors contained in each memory cell in one row has a normal threshold voltage. Likewise, to examine whether or not the other of the two inverter transistors contained in each memory cell in one row has a normal threshold voltage, inverted data of that for examining whether or not the above-mentioned inverter transistor has a normal threshold voltage is applied to each memory cell in advance. Accordingly, if all the memory cells in one row are simultaneously tested, all the inverter transistors contained therein are checked for their threshold voltage in 10 ms .times. 2, or 20 ms. Therefore, to check the inverter transistors in all the memory cells contained in one SRAM for their threshold voltage, the disturb test is conducted taking 20 ms for each row in the memory cell array.
In order to avoid the reduction in operating speed of SRAM's which is caused by an increased number of memory cells contained in a single SRAM, and achieve a higher-speed operation of SRAM's, large-capacity SRAM's generally have a memory cell array divided into a plurality of blocks which operate independently of one another. The disturb test as described above is performed for each block in such a block-divided type SRAM to check the threshold voltage of the inverter transistors in all the memory cells contained therein.
For a completed SRAM, there are several other tests to be conducted besides the disturb test. As one of such tests, possible disconnection of the two high resistances contained in a memory cell is examined. For this test, Japanese Patent Laying-Open No. 61-280095 describes a method of reducing the test time by performing data writing to the memory cells for testing, with a supply potential lower than usual being supplied to the bit lines.
The progress in fabrication technology of semiconductor integrated circuits and the demand of users for lower prices have accelerated the development of highly integrated SRAM's, increasing the integration level at the rate of about fourfold for 3 years, so that SRAM's of 1M (10.sup.6)-bit capacity are now being put to practical use. This leads to, however, increased test times taken for determining whether or not each memory cell functions properly.
Generally, when a memory cell does not function at all, the failure can be identified in a relatively short time. However, when such a functional failure is caused by a combination of several conditions such as ambient temperature of the memory cells, operation cycle of supply voltage, patterns of data written in a plurality of memory cells, and addressing order for the memory cells, it takes a considerable time only to identify such conditions and then to perform several tests. Especially for the time taken by the actual tests that are performed after the identification of conditions, it takes generally more and more time in proportion to the increasing number of memory cells contained in a single SRAM. The above-mentioned disturb test is among those tests involved in such a problem.
Assume, for example, that the disturb test as described above is applied to a 1M-bit SRAM having a memory cell array divided into 32 blocks. The time required to check the threshold voltage of the inverter transistors in all the memory cells is given by the expression; the row number in one block (256 rows) .times. the time required to check the threshold voltage of the inverter transistors contained in one-row memory cells in one block (20 ms) .times. the block number (32 blocks), or 16.4 seconds. This means that it takes a relatively long time, 16.4 seconds to perform only one test for a single SRAM. The thus increased time required for one test will inevitably increase the time taken for a series of tests applied to a completed large-capacity SRAM.
Meanwhile, a method of detecting a semiconductor integrated circuit device with abnormal characteristics through a simple short-time test has been recently proposed, for example, in U.S. Ser. No. 487,055. In this method, the substrate voltage of a semiconductor integrated circuit device is switched between test operation mode and normal operation mode.
Further, a conventional SRAM may comprise two power terminals. One power terminal receives a voltage for driving the memory cell portion. The other power terminal receives a voltage for driving a peripheral circuit of the memory cell portion. Such an SRAM is described in the document titled "1977 Mitsubishi Integrated Circuit Databook &lt; LSI &gt;" Vol. 5 pp. 3-6.